Embedded systems engineer specializing in FPGA design, looking to further his skills by developing reliable, high-performance systems that advance the state of the art.


Research Engineer - Driver Assist Technologies
Ford Motor Company (Dearborn, MI)
January 2017 - present

Embedded Systems Engineer
RHK Technology & Sonic Alert (Troy, MI)
April 2013 โ€“ January 2017

Developed FPGA firmware in VHDL and Verilog for scanning probe microscope controllers. Implemented communications interfaces, peripheral controllers, PI control loops, and DSP elements, including FIR and IIR filters, CORDICs, NCOs, and ALUs. Extensive experience with timing analysis and closure. Driver development in Forth.

Isolated sources of error in high-speed DAC & ADC interfaces used for piezoelectric control. Built a novel architecture-sympathetic delta-sigma modulator to improve conversion resolution while mitigating non-linearities.

Project manager for R&D lab based at Oakland University. Supervised development of several FPGA design projects, including a native Forth soft processor, and a reconfigurable signal routing system.

Lead engineer for a low-cost wireless home signaling system for the hearing impaired. Led development of C firmware for central unit and several remote sensor units. Developed custom mesh protocol operating on the ISM radio band, and worked with RF engineering team to ensure FCC compliance. Supervised production in Shenzhen, China. Developed software for production automation & testing.

Designed C firmware for Bluetooth-based signaling devices, along with accompanying iOS and Android applications. Experience with Apple Xcode (Swift and Objective-C) and Android Studio (Java).

Managing Partner
MicroNova LLC (Waterford, MI)
May 2012 โ€“ present

Designed a Xilinx Spartan-3A FPGA prototyping module in a compact DIP form-factor, with onboard ADC, SRAM, and 5V-tolerant I/O circuitry. Designed companion boards with audio, VGA and PS/2 interfaces. Implemented USB-to-SPI flash programming app in Visual C#. Wrote demo applications in VHDL. Xilinx Artix-7 FPGA module in development.

Set up US-based SMT assembly line with Mirae MPS-1030 pick & place machines, solder stencil printer, and reflow oven.

Engineering Intern
RHK Technology (Troy, MI)
September 2010 โ€“ April 2013

Built custom Ethernet controller with UDP and IP layers implemented in VHDL to accelerate throughput of microscope imaging data, and reduce command latency. Software driver in Forth. Testing with Wireshark and MATLAB.

Built digital phase shifter based on an Hilbert bandpass filter, to control an atomic force microscope (AFM) cantilever via self-oscillation control mode. FIR filter prototyping and analysis using MATLAB.

Built polynomial time generator (PTG) system for non-linear piezoelectric control, to improve microscope scan time and image quality.

Research & Teaching Assistant
Oakland University (Rochester, MI)
January 2010 โ€“ April 2013

Research assistant in Dr. Darrin Hanna's High-Performance Embedded Systems Lab. Researched methods of generating special-purpose hardware from stack-based intermediate representations of high-level software languages (e.g. Java-to-VHDL, C#-to-Verilog, etc).

Lab instructor and guest lecturer for microcontroller design course (C and HCS12 assembly with CodeWarrior) and FPGA digital logic and microprocessor design course (VHDL with Xilinx ISE).


B.S.E. Computer Engineering
Oakland University (Rochester, MI)
September 2007 โ€“ April 2011
GPA: 3.52
M.S. Embedded Systems
Oakland University (Rochester, MI)
September 2011 โ€“ April 2013
GPA: 3.66


  • Stereoscopic object tracking system based on a Spartan-6 FPGA. System detected a brightly colored object and computed X/Y position and approximate depth. Vision processing pipeline written in VHDL. Prototyping with MATLAB.
  • FPGA-based Mandelbrot/Julia fractal set explorer. Built several versions, including a highly-pipelined special-purpose processor with smart dispatcher written in VHDL, and a hybrid system using the Altera Nios II soft processor.
  • VGA graphics controller. Built several versions, including a bit-banging method using HCS12 assembly, a hybrid system for the Cypress PSoC-1, and a Verilog version tested on FPGA and fabricated on a 1mm x 1mm VLSI chip on MOSIS 0.5ยตm process.
  • Software-defined LF radio transceiver with ASK and PSK modem, based on a Cypress PSoC-1.
  • Levitating ping pong ball using a fuzzy control loop, implemented on HCS12 microcontroller in C and assembly.


Fluent: Embedded C, VHDL, Verilog, HCS12 assembly
Proficient: Forth, C#, Swift, Java, Cypress M8C assembly
Learning: Python, Objective-C, m68k assembly
Fluent: Altera Quartus II, Xilinx ISE, Aldec ActiveHDL, Microchip MPLAB X, Atmel Studio, Freescale CodeWarrior, Microsoft Visual Studio, Cypress PSoC Designer, Apache SVN
Proficient: Linux CLI, MATLAB, Apple Xcode, Android Studio, ModelSim, Wireshark
Learning: GNU Toolchain, Git, Altium Designer, Mentor Graphics IC Station, Cadence PSpice, Simulink


Darrin Hanna, Bryant Jones, Lincoln Lorenz, and Mark Bowers, "Flexible Embedded System Design using Flowpaths," Proceedings of the 2011 International Conference on Embedded Systems and Applications, Las Vegas, NV, July 18-21, 2011. (PDF)

Darrin Hanna, Bryant Jones, Lincoln Lorenz, and Mark Bowers, "Generating Hardware from Java Using Self-Propagating Flowpaths," Proceedings of the 2011 International Conference on Embedded Systems and Applications, Las Vegas, NV, July 18-21, 2011. (PDF)